As science and technology develop day by day, more and more common functions (e.g., audio processing, video processing, USB/DDR processing, and power management) are integrated on one chip, referred to as a system-on-chip, i.e., an SOC. A Σ-Δ modulator widely applied to audio analog-to-digital (DA) converting and radio frequency (RF) receiving fields may also be integrated with the SOC system.
The Σ-Δ modulator for converting an analog signal into a digital signal via over-sampling comprises an integrator, a quantizer, and a digital-to-analog converter (DAC). FIG. 1 shows a schematic diagram of a conventional single-path one-stage Σ-Δ modulator. An adder subtracts a feedback signal Vfb outputted by a DAC 300 from an input signal Vin to obtain a signal represented by (a1*Vin−b1*Vfb), where a1 and b1 are gain factors. The obtained signal is received and integrated by an integrator 100 to obtain an integrated signal that is transmitted to a quantizer 200. The quantizer 200 quantizes the integrated signal to obtain a digital signal Yout, which is converted by the DAC 300 into an analog signal that is then fed to the adder.
FIG. 2 shows a schematic circuit diagram of a single-path one-stage Σ-Δ modulator in the prior art. On top of the quantizer 200 and the DAC 300, the one-stage Σ-Δ modulator further comprises an op-amp 500, a sampling component Cs, an integrating component CI, and switches S1 to S4. Supposing that the op-amp 500 is in an ideal operating state, and the switches S1 to S4 are respectively controlled by two non-overlapped clocks P1 and P2. During a first period of a clock cycle, the clock signal P1 is at a high level, and the clock signal P2 is at a low level. At this point, the switches S1 and S3 are closed, and the switches S2 and S4 are open. During a second period of the clock cycle, the clock signal P1 is at a low level, and the clock signal P2 is at a high level. At this point, the switches S1 and S3 are open, and the switches S2 and S4 are closed. Detailed descriptions are given with reference to FIG. 3 and FIG. 4. Referring to FIG. 3, during the first period of the clock cycle, the sampling component Cs samples the input signal Vin via the switches S1 and S3, such that a voltage between two ends of the sampling component Cs is Vi[n−1]. At this point, the op-amp 500 is inactive, and a voltage at an output end of the op-amp 500 is maintained as Vo[n−1]. Referring to FIG. 4, during the second period of the clock cycle, a sampling component Cs, the op-amp 500 and the integrating component CI are coupled in sequence. Being affected by a feedback effect of the op-amp 500, charges of the sampling component Cs charged during the first period of the clock cycle are shifted to the integrating component CI, and a voltage at an output end of the op-amp 500 is calculated as:
            Vo      ⁡              [        n        ]              =                  Vo        ⁡                  [                      n            -            1                    ]                    +                        Ccs          Cci                ⁢                  Vi          ⁡                      [                          n              -              1                        ]                                ,where Ccs is a capacitance value of the component Cs, and Cci is a capacitance value of the component CI. In addition, a Z-transform of the foregoing equation is:
      Vo    ⁡          (      z      )        =            Ccs      Cci        *                            z                      -            1                                    1          -                      z                          -              1                                          .      Accordingly, the circuit structure in FIG. 2 can realize a principle illustrated in FIG. 1.
The Σ-Δ modulator is widely applied as a contribution of having a simple structure and a high conversion accuracy, and various types of multi-stage modulators are accordingly developed. FIG. 5 and FIG. 6 show schematic diagrams of a conventional single-path two-stage Σ-Δ modulator. The single-path two-stage Σ-Δ modulator comprises a first-stage integrating circuit and a second-stage integrating circuit, and an operating principle of the single-path two-stage Σ-Δ modulator is similar to that of the single-path one-stage Σ-Δ modulator in FIG. 2 and shall not be described for brevity. Compared to other components, op-amps 502 and 504 as main components of the integrating circuit consume most resources of area and power consumption of an overall system. Through a current technique, a size of the second stage op-amp 504 (even op-amps after the second stage op-amp) is manufactured to be much smaller than that of the first stage op-amp 502, so as to effectively reduce area and power consumption of the overall system. However, the single-path two stage Σ-Δ modulator still has numerous disadvantages. For example, the first stage op-amp of an one-stage or multi-stage modulator is disadvantaged by having large area, high power consumption, and high cost; op-amps are operated only during a half of the clock cycle, and are left idle during another half of the clock cycle to cause a waste of resources.
In order to solve the foregoing problem that the op-amps are left idle, a technique of a two-stage integrating circuit sharing an op-amp is provided. FIG. 7 shows a single-path two-stage Σ-Δ modulator sharing an op-amp in the prior art. The single-path two-stage Σ-Δ modulator comprises an integrator 102, an integrator 104, and an op-amp 506 shared by the integrators 102 and 104. During a first period of a clock cycle, the op-amp 506 is connected to the integrator 102 to serve as a first-stage integrating circuit. During a second period of the clock cycle, the op-amp 506 is connected to the integrator 104 to serve as a second-stage integrating circuit. Operation details of the op-amp 506 connected to the integrator 102 or the integrator 104 are similar to those of the op-amp 500 of the single-path one-stage Σ-Δ modulator in FIG. 2, and shall not be described for brevity. The approach of sharing one op-amp by two stages of integrating circuits is capable of reducing the number of the op-amps as well as reducing area and power consumption of the overall system to some extent; nevertheless, a problem of crosstalk is incurred meanwhile.
FIG. 8 shows a schematic diagram of a two-stage integrating circuit with the shared op-amp 506, in which crosstalk is incurred. Under ideal circumstances, a gain of an op-amp under an ideal operating conditions approaches infinity, such that a voltage at a negative input end of the ideal op-amp equals a voltage at a positive input end. However, in practical applications, the gain and a bandwidth of the op-amp 506 are limited. During a first period of a clock cycle, when the op-amp 506 is connected to the integrating circuit CI, the first-stage integrating circuit performs integration, and at this point a residual voltage Vr is left at the negative input end of the op-amp 506, such that a parasitic capacitor Cr at the negative input end of the op-amp 506 is stored with an amount of residual charge Qr represented by Qr=Cr×Vr. Therefore, during a second period of the clock cycle, the residual charge Qr enters a second-stage integrating circuit to incur crosstalk, and thus a transfer function of the Σ-Δ modulator is changed to cause performance deterioration due to the noises.
In addition, in a two-stage integrating circuit that does not adopt the shared op-amp technique, since a size of an op-amp of a second-stage integrating circuit is already much smaller than that of an op-amp of a first-stage integrating circuit, the reduced amount of chip area is not obvious when the op-amp of the first-stage integrating circuit is shared by the second-stage integrating circuit. Accordingly, current various multi-paths multi-stage Σ-Δ modulators does not implement the op-amp sharing technique.
In conclusion, there is a need for a solution applying the op-amp sharing technique to a multi-path multi-stage Σ-Δ modulator to yield better overall performance.